N-type metal-oxide-silicon (NMOS) transistors such as transistor 100 of FIG. 1 are a frequent choice for ESD protection circuits for integrated circuits. Transistor 100 comprises N-type source and drain regions 110, 120 in a P-type well 130 in substrate 140, an insulating layer 150 on the substrate and a gate 160 on the insulating layer between the source and drain regions. Sidewall spacers 162 are located on each side of gate 160; and lightly doped drain (LDD) regions 170, 180 extend part way under the gate from the source and drain regions. Transistor 100 operates to provide ESD protection by triggering a parasitic lateral bipolar transistor 190 inherent in the MOS structure where the source and drain regions 110, 120 of the MOS transistor constitute the emitter and collector of the lateral bipolar transistor and the well 130 constitutes the base. See, for example, A. Amerasekera et al., ESD in Silicon Integrated Circuits, pp. 81-95 (2d Ed., Wiley, 2002), which is incorporated herein by reference.
In an integrated circuit (IC), a typical implementation of a MOS transistor is as a multi-fingered gate structure 200 such as that shown in a top view in FIG. 2A and in cross-section in FIG. 2B taken along line B-B of FIG. 2A. For convenience, only four of the fingers of the device of FIG. 2A have been shown in FIG. 2B. Structure 200 comprises N-type source and drain regions 210, 220 in a P-type substrate 230 over a deep N-type well 240, an insulating layer 250 on the substrate and a multi-fingered gate 260 on the insulating layer. LDD regions 270, 280 extend part way under each gate finger. As depicted schematically in FIG. 2A, the source regions 210 are connected together by a connector 215 that is typically formed in a metallization layer on the IC; the drain regions 220 are connected together by a connector 225 also formed in a metallization layer on the IC; and the gate fingers are connected together by a connector 265 also formed in a metallization layer on the IC. As a result, the source regions, the drain regions and the gate fingers are each connected in parallel. The dimension L is the gate length; the dimension W is the width of a gate finger. Since the source regions, the drain regions and the gate fingers are connected in parallel, the total gate width of the transistor is the product of W and the number of fingers, or 8 W for the device shown in FIG. 2A.
Structure 200 further includes a N-type implant region 290 that circumscribes multi-fingered gate structure 200 on the periphery of the structure; an N-type contact (or tap) 292; and a P-type contact (or tap) 232 located between the gate fingers and the N-type tap 292. N-type tap 292 makes ohmic contact to N-type well 240 through N-type implant region 290; and P-type tap 232 makes ohmic contact to P-type substrate 230.
In an ESD protection circuit, the P-type tap 232 is formed on all four sides of the multi-fingered transistor as shown in FIG. 2A. However, there is considerable variation in distance between the P-type tap 232 and the different portions of the gate fingers of the multi-fingered transistor. As a result, the electric potential of the substrate under the different gate fingers varies along the different fingers. Since the triggering of the parasitic bipolar transistor depends on forward biasing the P-N junction between the P-type substrate and the N-type source region, the potential difference at some portions of the multi-fingered structure between the substrate and the adjacent source regions may not be enough to trigger the parasitic transistor in those portions. Thus, triggering of the transistor tends to be non-uniform with the result that the transistor is not able to discharge as large an ESD pulse as it could if triggering were substantially uniform across the entire multi-fingered structure.
Conventional efforts to increase the potential difference between the substrate and the source under the gate fingers usually involve increasing the distance between these regions and the P-type tap. The penalty for this, however, is that there is a substantial gap 235 between the gate fingers and the P-type substrate tap resulting in an increase in the size of the transistor.